AMD has started ramping production of its next-generation EPYC processor, codenamed Venice, on TSMC's 2nm process technology.
Venice is AMD's sixth-generation EPYC data centre CPU, and the production ramp marks a key step in its server processor roadmap. Production is ramping in Taiwan, with manufacturing also planned for TSMC's Arizona site.
AMD said Venice is the industry's first high-performance computing product to enter production on TSMC's advanced 2nm node. The announcement comes as chipmakers and cloud infrastructure suppliers seek more computing capacity for AI systems, including increasingly complex agentic AI workloads.
CPUs remain central to AI data centres, handling data movement, networking, storage, security and system orchestration. That role has become more prominent as AI deployments expand beyond model training and inference into more distributed and demanding workloads.
AMD is using the Venice ramp to reinforce its position in the server market, where EPYC processors compete with Intel's Xeon line and Arm-based offerings used by major cloud groups. The move to a new manufacturing node is also closely watched because process advances can affect power consumption, chip density and overall performance in data centre hardware.
Manufacturing footprint
Starting production in Taiwan while preparing output in Arizona reflects a broader industry effort to diversify semiconductor manufacturing. For AMD, which relies on external foundries rather than operating its own fabs, access to advanced process technology and sufficient capacity remains central to serving data centre customers.
TSMC is the dominant contract chipmaker for leading-edge semiconductors and a critical supplier to companies building processors for AI, cloud computing and high-performance systems. AMD said its work with TSMC extends beyond the 2nm process to advanced packaging methods, including SoIC-X and CoWoS-L, which are used across its AI and data centre products.
Lisa Su, Chair and Chief Executive Officer of AMD, linked the latest production step to rising demand for AI infrastructure. "Ramping 'Venice' on TSMC 2nm process technology marks an important step forward in accelerating the next generation of AI infrastructure," Su said.
"As AI and agentic workloads scale rapidly, customers need platforms that can move from innovation to production faster. Our deep partnership with TSMC is helping AMD bring leadership compute technologies to market with the speed and scale required to meet this moment," she added.
Next products
Alongside Venice, AMD plans to extend its use of the 2nm process in its data centre CPU line with a follow-on product called Verano. The processor will include LPDDR memory integration, a design choice aimed at supporting cloud and AI computing workloads, where memory bandwidth and power consumption are becoming more important constraints.
That points to a broader shift in the server market. As AI systems grow larger and more distributed, chip designers are paying closer attention not only to raw processor speed but also to memory architecture, data transfer and energy use across entire server platforms.
For TSMC, AMD's production milestone is another example of early customer adoption of its latest manufacturing technology. The foundry has been central to efforts by major US chip designers to secure access to the most advanced nodes as competition intensifies in AI semiconductors.
C.C. Wei, Chairman and Chief Executive Officer of TSMC, said the partnership reflects how demand for advanced manufacturing and chip design is advancing in tandem. "We are pleased to see AMD continue to make strong progress with its next-generation EPYC processor on our advanced 2nm process technology," Wei said.
"Our close collaboration with AMD reflects the importance of pairing leadership process technology with advanced design innovation to enable the next era of high-performance and AI computing," he added.